[1]王浩,谢文明,蔡思静,等.应用于中高速SAR ADC的低功耗少开关开关方法[J].福建工程学院学报,2016,14(06):593-596.[doi:10.3969/j.issn.1672-4348.2016.06.016]
 Wang Hao,Xie Wenming,Cai Sijing,et al.Low-power consumption switching scheme with reduced switches for medium-or high-speed SAR ADCs[J].Journal of FuJian University of Technology,2016,14(06):593-596.[doi:10.3969/j.issn.1672-4348.2016.06.016]
点击复制

应用于中高速SAR ADC的低功耗少开关开关方法()
分享到:

《福建工程学院学报》[ISSN:2097-3853/CN:35-1351/Z]

卷:
第14卷
期数:
2016年06期
页码:
593-596
栏目:
出版日期:
2016-12-25

文章信息/Info

Title:
Low-power consumption switching scheme with reduced switches for medium-or high-speed SAR ADCs
作者:
王浩 谢文明 蔡思静 郑少锋
福建工程学院 信息科学与工程学院
Author(s):
Wang Hao Xie Wenming Cai Sijing Zheng Shaofeng
College of Information Science and Engineering, Fujian University of Technology
关键词:
低功耗 少开关 开关方法 SAR ADC
Keywords:
low-powerreduced switchswitching schemesuccessive approximation register analog-to-digital converter(SAR ADCs)
分类号:
TN43
DOI:
10.3969/j.issn.1672-4348.2016.06.016
文献标志码:
A
摘要:
提出一种应用于中高速逐次逼近型模数转换器(successive approximation register analog-to-digital converter,SAR ADC)的低功耗开关方法,该开关方法不需要额外的基准产生电路,并且需要的开关数量最少。使用重置序列(0 1…1)而不是(1 1…1)可以使得第2个位转换周期消耗的开关能量为0。为了进一步降低功耗,参考电容C使用C/2(两个C串联)并联来实现,这样所需要的C的数量又减少了将近一半,开关功耗又减少了一半。在同样的开关数量下,提出的开关方法消耗开关能量和需要的电容面积最小
Abstract:
A low-power switching scheme for medium-or high-speed successive approximation register analog-to-digital converter(SAR ADCs)was proposed, which requires the fewest switches but does not need extra reference generation circuit. By resetting series (0 1…1) rather than (1 1…1), no switching energy was consumed during the second bit cycle. To further reduce the switching energy, C was realized by two C/2 in parallel where C/2 is two Cs in series. The required number of C and the switching energy were nearly reduced by half. The results indicate that the proposed switching method is the most energy-efficient and area-efficient with the fewest switches.

参考文献/References:

[1] Liu C C, Chang S J, Huang G Y, et al. A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure[J]. IEEE Journal of Solid-State Circuits,2010,45(4):731-740.
[2] Zhu Y, Chan C H, Chio U, et al. A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS[J]. IEEE Journal of Solid-State Circuits,2010,45(6):1111-1121.
[3] Yuan C, Lam Y. Low-energy and area-efficient tri-level switching scheme for SAR ADC[J]. Electronics Letters,2012,48(9):482-483.
[4] Liou C Y, Hsieh C C. A 2.4-to-5.2 fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with charge-average switching DAC in 90nm CMOS[C]// IEEE International Solid-State Circuits Conference Digest of Technical Papers(ISSCC),2013:280-281.
[5] Sanyal A, Sun N. SAR ADC architecture with 98% reduction in switching energy over conventional scheme[J]. Electronics Letters,2013,49(4):248-250.
[6] Xie L, Wen G, Liu J, et al. Energy-efficient hybrid capacitor switching scheme for SAR ADC[J]. Electronics Letters,2014,50(1):22-23.
[7] Cao Z, Yan S, Li Y. A 32 mW 1.25 GS/s 6b 2b/Step SAR ADC in 0.13μm CMOS[J]. IEEE Journal of Solid-State Circuits,2009,44(3):862-873.

更新日期/Last Update: 2016-12-25