参考文献/References:
[1] Liu C C, Chang S J, Huang G Y, et al. A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure[J]. IEEE Journal of Solid-State Circuits,2010,45(4):731-740.
[2] Zhu Y, Chan C H, Chio U, et al. A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS[J]. IEEE Journal of Solid-State Circuits,2010,45(6):1111-1121.
[3] Yuan C, Lam Y. Low-energy and area-efficient tri-level switching scheme for SAR ADC[J]. Electronics Letters,2012,48(9):482-483.
[4] Liou C Y, Hsieh C C. A 2.4-to-5.2 fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with charge-average switching DAC in 90nm CMOS[C]// IEEE International Solid-State Circuits Conference Digest of Technical Papers(ISSCC),2013:280-281.
[5] Sanyal A, Sun N. SAR ADC architecture with 98% reduction in switching energy over conventional scheme[J]. Electronics Letters,2013,49(4):248-250.
[6] Xie L, Wen G, Liu J, et al. Energy-efficient hybrid capacitor switching scheme for SAR ADC[J]. Electronics Letters,2014,50(1):22-23.
[7] Cao Z, Yan S, Li Y. A 32 mW 1.25 GS/s 6b 2b/Step SAR ADC in 0.13μm CMOS[J]. IEEE Journal of Solid-State Circuits,2009,44(3):862-873.